1. Field of the Invention
The present invention relates to methods for providing, in a clock generation or distribution circuit, a synchronous delay in an output clock signal relative to a synchronization signal.
2. Discussion of the Related Art
Clock generation or distribution circuits are often required to synchronize its output signals relative to a reference synchronization signal. It is also often desirable to delay one output signal relative to another to achieve specific objects, such as to optimize set-up and hold times, or to create quadrature (90° phase shifted) signals. The required delay may be provided as a fine “analog” delay or a coarse but accurate “digital” delay. An analog delay is usually achieved by adding gate propagation delays in small steps. Consequently, such delays are generally difficult to control to precision, especially the circuit operates over a wide temperature range. In contrast, the digital delay may be controlled to greater precision and is repeatable. Often, the digital delay is provided by an integer number of periods of the input clock signal.
FIG. 1 illustrates a method for providing a digital delay in an output signal relative to synchronization signal SYNC in clock frequency division circuit 100. As shown in FIG. 1, clock frequency division circuit 100 includes divider 101, delay counter 102, and output flip-flop 103. In clock frequency division circuit 100, when synchronization signal SYNC becomes active, delay counter 102 counts down from an initially loaded delay value. Until delay counter 102 reaches zero, delay counter 102 holds divider 101 in a reset mode by asserting a “wait” signal at terminal 104. When delay counter 102 reaches zero, delay counter 102 de-asserts the wait signal at terminal 104 to enable divider 101 to provide a valid output signal, which is then synchronized with the input clock signal by output flip-flop 103. Under this approach, delay counter 102 operates at the same frequency as divider 101, and thus poses the same level of design difficulty—and is similarly power-intensive—as divider 101. Furthermore, delay counter 102 requires additional silicon area, which may be as much as the silicon area occupied by divider 101.